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容易理解eMMC存储器半导体的开发(eMMC 메모리 반도체 개발을 쉽게 이해하기)

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분야기타 > 과학/IT
작가金荣民(김영민)
출판형태종이책
페이지수 295 Pages
인쇄컬러표지-컬러, 내지-흑백
판형 A4
출판사부크크
ISBN979-11-372-1579-5
출판일2020.08.25
총 상품 금액 30,000

저자 소개

作者 金荣民

前三星电子半导体事业部商品企划组(eMMC负责)
前Hynix Storage开发组(负责eMMC开发)

网页 http://easyrun.co.kr

번역자 소개 (번역서인 경우 입력해주세요.)

목차

目录

1. eMMC 概要 20
1-1. eMMC System 概要 20
1-2. System 特点 20
1-3. System 动作电压构成 21
1-4. 基本动作电压的Timing说明 21
1-5. Bus Protocol 22
1-6. Register 种类 23
1-6-1. CID Fields : 16 bytes 23
1-6-2. RCA register : 2 bytes 24
1-6-3. DSR register content : 2 bytes 24
1-6-4. CSD Fields 24
1-6-5. OCR register 25
1-6-6. EXT_CSD fields : 512 bytes 26
1-7. 动作指令 31
1-8. 主要 State diagram 34
1-8-1. eMMC state diagram (boot mode) 34
1-8-2. eMMC state diagram (Card identification mode) 34
1-8-3. eMMC state diagram (data transfer mode) 35
1-8-4. eMMC state transition diagram, interrupt mode 36
1-9. Multiple-block의 CMD, Data 之间的基本动作 36
1-9-1. Multiple-block read operation 36
1-9-2. Multiple-block write operation 36
1-9-3. No ‘response’ and ‘no data’ operations 37

2. eMMC Hardware 38
2-1. Power supply 38
2-1-1. eMMC eMMC internal power diagram 38
2-1-2. e2MMC internal power diagram 38

2-2. High Speed System Block diagram 39
2-2-1. HS200 System Block diagram 39
2-2-2. HS400 System Block diagram 40

2-3. eMMC Power-up 40
2-3-1. eMMC voltage combinations 40
2-3-2. Power supply Voltages 41
2-3-3. Power-up 41
2-3-4. Power-up diagram 41
2-3-5. eMMC power-up diagram 43
2-3-6. eMMC power-up guidelines 43
2-3-7. eMMC power cycle 44

2-4. eMMC bus 45
2-4-1. Bus circuitry diagram 45
2-4-2. Bus signal levels 46
2-4-3. Programmable Card output driver 47
2-4-4. DSR register content 47
2-4-5. eMMC bus driver 47
2-4-6. Bus signal line load 48
2-4-7. Capacitance and Resistors 49
2-4-8. Bus general operating conditions 49
2-4-9. High-speed eMMC bus functions 50
2-4-9-1. Bus initialization 50
2-4-10. Bus Operating Conditions for HS200 and HS400 51
2-4-11. Card Output Driver Requirements for HS200 and HS400 51
2-4-11-1. Driver Types Definition 51
2-4-11-2. I/O driver strength types 51
2-4-12. Driver Type-0 AC Characteristics 52
2-4-12-1. Driver Type-0 AC Characteristics 52
2-4-12-2. Driver Type-0 Test Circuit 52
2-4-12-3. Outputs test circuit for rise/fall time measurement 52
2-4-13. Driver Type Selection 52

2-5. Bus Speed Modes 53
2-5-1. eMMC提供的多样的Bus Speed模式 53
2-5-2. High Speed mode 特点 53
2-5-3. 数据Bus width 变更 53
2-5-4. XNOR values 54
2-5-5. Switching to high-speed mode 54
2-5-6. Speed class definition 54
2-5-7. Measurement of the performance 55

2-6. Block operation 55
2-6-1. Multiple-block operation 55
2-6-1-1. Multiple-block read operation 56
2-6-1-2. Multiple-block write operation 56
2-6-1-3. No ‘response’ and ‘no data’ operations 56

2-7. Token format 概念 57
2-7-1. Command token format : 命令代币牌形式 57
2-7-2. Response token format 57
2-7-3. SDR (Single Data Rate)用 Data packet format 58
2-7-3-1. 1 Bit bus (only DAT0 使用) 58
2-7-3-2. 4 Bits bus (DAT0 ~ DATA3 使用) 58
2-7-3-3. 8 Bits bus (DAT0 ~ DAT7 使用) 58
2-7-4. DDR (Double Data Rate)用 Data packet format 59
2-7-4-1. 4 Bit bus DDR (DAT0 ~ DAT3 使用) 59
2-7-4-2. 8 Bit bus DDR (DAT0 ~ DAT7 使用) 60
2-7-4-3. 8 Bit bus DDR for HS400 output (DAT7 ~ DAT0 使用) 61
2-7-5. DDR52用 CRC status token 62
2-7-5-1. Positive CRC status token (‘010’) 或Boot认知模式时 62
2-7-5-2. Negative CRC status token (‘101’) 时候 62
2-7-5-3. HS400用 status CRC token 63
2-7-5-4. Positive CRC status token (‘010’) 时候 63
2-7-6-5. Negative CRC status token (‘101’) 时候 63
2-7-6. Error conditions 64
2-7-6-1. CRC and illegal command 63

2-8. Timings 63
2-8-1. Clock control 64
2-8-2. Command and response 64
2-8-2-1. Identification timing (Card identification mode) 64
2-8-2-2. SET_RCA timing (Card identification mode) 64
2-8-2-3. Command response timing (data transfer mode) 65
2-8-2-4. R1b response timing 65
2-8-2-5. R1b Timing 65
2-8-2-6. Timing response end to next command start (data transfer mode) 65
2-8-2-7. Timing of command sequences (all modes) 66
2-8-3. Data read 66
2-8-3-1. Single-block read timing 66
2-8-3-2. Multiple-block read timing 66
2-8-3-3. Stop command timing (CMD12, data transfer mode) 67
2-8-3-4. Read ahead in multiple block read operation 67
2-8-3-5. Data Strobe Read Timing 67
2-8-3-6. HS400 Read Timing with data block size of 512 bytes 67
2-8-3-7. Read Block Gap 67
2-8-3-8. Clock Stop Timing at Block Gap in Read Operation 68
2-8-4. Data write 68
2-8-4-1. Block write command timing 69
2-8-4-2. Multiple-block write timing 69
2-8-4-3. HS400 Write Timing 69
2-8-4-4. HS400 Write Timing with data block size of 512 bytes 69
2-8-4-5. NCRC timing 69
2-8-4-6. BUSY Signal after CRC Status Response 70
2-8-5. Stop transmission 70
2-8-5-1. Stop transmission during data transfer from the host 70
2-8-5-2. Stop transmission during CRC status transfer from the Card 70
2-8-5-3. Stop transmission after last data block; Card is busy programming 71
2-8-5-4. Reselecting a Busy Card 71
2-8-5-5. Stop transmission after last data block; Card becomes busy 71
2-8-5-6. Stop transmission timing 72
2-8-5-7. Stop transmission just before CRC status transfer from the Card 72
2-8-5-8. Stop transmission during CRC status transfer from the Card - 1 72
2-8-5-9. Stop transmission during CRC status transfer from the Card - 2 72
2-8-6. CMD12 Timing Modification 73
2-8-6-1. CMD12 Timing Modification in Write Operation 73
2-8-6-2. Border Timing of CMD12 in Write Operation 73
2-8-6-3. CMD12 Timing Modification in Read Operation 73
2-8-6-4. Border Timing of CMD12 in Read Operation 74
2-8-7. Enhanced Strobe in HS400 Mode 74
2-8-7-1. Enhanced Strobe signals for CMD Response and Data Out (Read operation) 74
2-8-7-2. Enhanced Strobe signals for CMD Response and CRC Response (Write operation) 74
2-8-7-3. HS400 mode change with Enhanced Strobe 74
2-8-8. Bus test procedure timing 75
2-8-8-1. Bus test procedure timing 75
2-8-9. Boot operation 75
2-8-9-1. Boot operation, termination between consecutive data blocks 75
2-8-9-2. Boot operation, termination during transfer 75
2-8-9-3. Bus mode change timing (push-pull to open-drain) 76
2-8-10. Alternative boot operation 76
2-8-10-1. Alternative boot operation, termination between consecutive data blocks 76
2-8-10-2. Alternative boot operation, termination during transfer 76

2-9. High speed Timing Values 77
2-9-1. Timing Parameters 77
2-9-2. Timing changes in HS200 and HS400 mode 77
2-9-2-1. Timing values 77
2-9-2-2. Timing Parameters for HS200 and HS400 mode 77
2-9-2-3. Timing diagram : data input / output in single data rate mode 78
2-9-3. Card interface timings 78
2-9-3-1. High-speed Card interface timing 78
2-9-4. Bus Timing Specification in HS200 mode 79
2-9-4-1. HS200 Clock Timing 79
2-9-4-2. HS200 Clock signal timing 79
2-9-4-3. HS200 Clock signal timing table 79
2-9-4-4. HS200 Card Input Timing 80
2-9-4-5. HS200 Card input timing table 80
2-9-4-6. HS200 Card Output Timing 80
2-9-4-7. HS200 Card output timing table 81
2-9-4-8. ∆TPH consideration 81
2-9-5. Bus Timing Specification in HS400 mode 82
2-9-5-1. HS400 Card Input Timing 82
2-9-5-2. HS400 Card input timing table 82
2-9-5-3. HS400 Card Output Timing 83
2-9-5-4. HS400 Card output timing table 83
2-9-5-5. HS400 Capacitance and Resistors 84
2-9-5-6. HS400 Card Command Output Timing 84
2-9-5-7. HS400 CMD Response timing 84
2-9-5-8. HS400 CMD Response timing table 85
2-9-5-9. HS400 reference load 85

2-10. Host Forward/Backward-compatible Card interface timing 85
2-10-1. Forward-compatible host interface timing 86
2-10-2. Backward-compatible Card interface timing 86
2-10-3. Timing diagram : data input / output in dual data rate mode 87
2-10-4. Bus timing for DAT signals during 2x data rate operation 87
2-10-5. High-speed Dual data rate interface timings 88
2-10-6. High-speed Card interface timing 88
2-10-7. Backward-compatible Card interface timing 89

2-11. AC Overshoot/Undershoot Specification 90
2-11-1. Overshoot/Undershoot definition 90

2-12. Partition management 90
2-12-1. Command restrictions 91
2-12-2. Boot partition 92
2-12-2-1. BOOT_SIZE_MULT [226] - EXT_CSD : Boot partition size 92
2-12-2-2. RPMB_SIZE_MULT [168] - EXT_CSD : RPMB Partition Size 93
2-12-3. Handling write protection for each boot area individually 93
2-12-4. Extended Partitions Attribute 94
2-12-5. Configure partitions 94
2-12-6. Flow chart for General Purpose Partitions & Enhanced User Data Area parameter setting 95
2-12-7. Memory array partitioning 97

2-13. Time-out conditions 98

2-14. Error protection 99
2-14-1. Error correction codes (ECC) 99
2-14-2. Cyclic redundancy codes (CRC) 99
2-14-3. CRC7 99
2-14-4. CRC7 generator/checker 100
2-14-5. CRC16 100
2-14-6. CRC16 generator/checker 100

2-15. Temperature Conditions 100
2-15-1. Temperature Conditions per Power Classes (Tcase controlled) 101
2-15-2. Heat Removal - Nomenclatures 101
2-15-3. Package Case Temp (Tc) per current consumption 102

2-16. eMMC standard compliance 102
2-16-1. eMMC host requirements for Card classes 102
2-16-2. New Features List for Card type 103

3. eMMC functional description 106
3-1. Operation mode, Card state, CMD line mode 关系 106
3-1-1. Open-drain mode bus signal level 106
3-1-2. Push-pull mode bus signal level 106
3-1-3. Push-pull signal level - high-voltage 107
3-1-4. Push-pull signal level - 1.70 V -1.95 V VCCQ voltage Range 107
3-1-5. Push-pull signal level - 1.1 V-1.3 V VCCQ range 107

3-2. Boot mode 107
3-2-1. Card reset to Pre-idle state 107
3-2-2. WP condition transition due to H/W reset assertion 108
3-2-2-1. RST_n signal at the power up period 108
3-2-2-2. H/W reset timing parameters 108
3-2-2-3. H/W reset waveform 109
3-2-2-4. Noise filtering timing for H/W Reset 109
3-2-3. Boot operation mode 109
3-2-3-1. Boot mode timing cycle 110
3-2-4. Alternative boot operation 110
3-2-4-1. Alternative boot mode timing cycle 111
3-2-5. Clarification of RESET_BOOT_BUS_CONDITIONS behavior when CMD0 is issued in IDLE 112
3-2-6. Access to boot partition 112
3-2-7. Boot bus width and data access configuration 113
3-2-8. Boot Partition Write Protection 113
3-2-9. Setting EXT CSD BOOT_WP [173] 113

3-3. Card identification mode 114
3-3-1. Card reset 114
3-3-2. Card identification mode state diagram 114
3-3-3. Access mode validation (higher than 2GB of densities) 115
3-3-4. From busy to ready 116
3-3-5. Card identification process 116

3-4. Interrupt mode 116
3-4-1. eMMC state transition diagram, interrupt mode 117

3-5. Data transfer mode 117
3-5-1. data transfer mode state diagram 117
3-5-2. Command sets and extended settings 118
3-5-3. EXT_CSD access mode 119
3-5-4. High speed modes selection 120
3-5-4-1. “High speed” mode selection 120
3-5-4-2. “HS200” timing mode selection 120
3-5-4-3. HS200 Selection flow diagram 121
3-5-4-4. “HS400” timing mode selection 121
3-5-4-5. HS400 Selection flow diagram 122
3-5-4-6. HS400 (Enhanced Strobe) Slection flow diagram 123
3-5-5. Power class selection 123
3-5-6. Bus testing procedure 124
3-5-6-1. Bus testing pattern 124
3-5-6-2. 1 bit bus testing pattern 124
3-5-6-3. 4 bit bus testing pattern 125
3-5-6-4. 8 bit bus testing pattern 125
3-5-6-5. Bus testing for eight data lines 125
3-5-6-6. Bus testing for four data lines 125
3-5-6-7. Bus testing for one data line 126
3-5-7. Bus Sampling Tuning Concept 126
3-5-7-1. Sampling Tuning Sequence for HS200 126
3-5-7-2. Send Tuning Command 126
3-5-7-3. Tuning block pattern for 8 bit mode 127
3-5-7-4. Tuning block on DAT[7:0]/DAT[3:0] in 8 bit/4 bit bus width 128
3-5-8. Bus width selection 129
3-5-9. Data read 129
3-5-9-1. Block read 129
3-5-10. Data write 130
3-5-11. Block write 131
3-5-12. Erase 132
3-5-12-1. Erase command (CMD38) Valid arguments 133
3-5-13. TRIM 133
3-5-14. Sanitize 134
3-5-15. Discard 134
3-5-16. Secure Erase 135
3-5-16-1. Erase command (CMD38) Valid arguments 135
3-5-17. Secure Trim 136
3-5-18. Write protect management 137
3-5-18-1. Write Protection Hierarchy (when diable bits are clear) 138
3-5-18-2. Write Protection Types (when diable bits are clear) 138
3-5-19. Extended Security Protocols Pass Through Commands 138
3-5-19-1. PROTOCOL_RD - CMD53 139
3-5-19-2. PROTOCOL_WR - CMD54 139
3-5-19-3. Security Protocols (class 10) 139
3-5-19-4. Security Protocol Type 139
3-5-19-5. Security Protocol Information 139
3-5-19-6. Error handling 140
3-5-20. Production State Awareness 140
3-5-20-1. Manual Mode 140
3-5-20-2. Auto Mode 141
3-5-20-3. Recommended Soldering procedure 141
3-5-21. Field Firmware Update 142
3-5-21-1. FFU flow 143
3-5-22. Card lock/unlock operation 144
3-5-22-1. Lock Card data structure 145
3-5-22-2. Setting the password 145
3-5-22-3. Reset the password 146
3-5-22-4. Locking the Card 146
3-5-22-5. Description of method for storing passwords on the Card 147
3-5-22-6. Handling of passwords 148
3-5-22-7. Changing the password 148
3-5-22-8. Removal of the password 148
3-5-22-9. Forcing erase 148
3-5-23. Application-specific commands 149
3-5-23-1. Sleep (CMD5) 150
3-5-24. Replay Protected Memory Block 150
3-5-24-1. Data Frame Files for RPMB 150
3-5-24-2. RPMB Request/Response Message Types 151
3-5-24-3. RPMB Operation Results data structure 151
3-5-24-4. RPMB Operation Results 151
3-5-24-5. Memory Map of the Replay Protected Memory Block 152
3-5-24-6. Message Authentication Code Calculation 153
3-5-24-7. MAC Example 153
3-5-24-8. Accesses to the Replay Protected Memory Block 154
3-5-24-9.. Programming of the Authentication Key 154
3-5-24-10. Authentication Key Data Packet 154
3-5-24-11. Result Register Read Request Packet 154
3-5-24-12. Response for Key Programming Result Request 155
3-5-24-13. Reading of the Counter Value 155
3-5-24-14. Counter Read Request Packet 155
3-5-24-15. Counter Value Response 156
3-5-24-16. Authenticated Data Write 156
3-5-24-17. Program Data Packet 156
3-5-24-18. Result Register Read Request Packet 157
3-5-24-19. Response for Data Programming Result Request 157
3-5-24-20. Authenticated Data Read 157
3-5-24-21. Data Read Request Initiation Packet 158
3-5-24-22. Read Data Packet 158
3-5-24-23. Authenticated Card Configuration Write 158
3-5-24-24. Authenticated Card Configuration Write packet 159
3-5-24-25. Response for Authenticated Card Configuration Write Request 159
3-5-24-26. Authenticated Card Configuration Read 160
3-5-24-27. Authenticated Card Configuration Read Initiation packet 160
3-5-24-28. Response for Authenticated Card Configuration Read 160
3-5-25. Dual Data Rate mode selection 161
3-5-26. Dual Data Rate mode operation 161
3-5-27. Background Operations 161
3-5-28. High Priority Interrupt (HPI) 162
3-5-28-1. Interruptible commands 162
3-5-28-2. HPI background and one of possible solutions 163
3-5-29. Context Management 164
3-5-29-1. Context configuration 164
3-5-29-2. Context direction 164
3-5-29-3. Large-Unit 165
3-5-29-4. Context Writing Interruption 165
3-5-29-5. Large-Unit Multipliers 166
3-5-30. Data Tag Mechanism 166
3-5-31. Packed Commands 167
3-5-31-1. Packed Command Header 167
3-5-31-2. Packed Command Structure 167
3-5-31-3. Packed Commands Error Handling 167
3-5-32. Exception Events 168
3-5-33. Cache 168
3-5-34. Features cross matrix 170
3-5-34-1. Features Cross Reference Table 170
3-5-35. Dynamic Capacity Management 171
3-5-36. Large sector size 172
3-5-36-1. eMMC internal sizes and related Units / Granularities 172
3-5-36-2. Disabling emulation mode 172
3-5-36-3. Native 4KB sector behavior 174
3-5-36-4. Admitted Data Sector Size, Address Mode and Reliable Write granularity 174
3-5-37. Real Time Clock Information 175
3-5-37-1. Real Time Clock Information Block Format 175
3-5-37-2. RTC_INFO_TYPE Field Description 175
3-5-37-3. Periodic Wake-up 175
3-5-38. Power Off Notification 176
3-5-39. Cache Enhancement Barrier 176
3-5-40. Cache Flushing Policy 177
3-5-41. Command Queuing 177
3-5-41-1. Overview 177
3-5-41-2. QUEUED_TASK_PARAMS - CMD44 178
3-5-41-3. QUEUED_TASK_ADDRESS - CMD45 178
3-5-41-4. EXECUTE_READ_TASK - CMD46 179
3-5-41-5. EXECUTE_WRITE_TASK - CMD47 179
3-5-41-6. CMDQ_TASK_MGMT - CMD48 179
3-5-41-7. Task Management op-codes 179
3-5-41-8. SEND_STATUS - CMD13 179
3-5-41-9. Error handling 179
3-5-41-10. Error handling for Command Queue 179
3-5-41-11. Supported Commands 180
3-5-41-12. Supported Commands for Command Queue 180
3-5-41-13. Secure Write Protect Mode 181
3-5-41-14. Card Configuration Area 181

4. Card Registers 182
4-1 OCR register 182
4-1-1. OCR register definitions 182

4-2. CID register 182
4-2-1. CID Fields 182
4-2-2. MID [127:120] 183
4-2-3. BIN [119:114] 183
4-2-4. CBX [113:112] 183
4-2-4-1. Card Types 183
4-2-6. PNM [103:56] 183
4-2-7. PRV [55:48] 183
4-2-8. PSN [47:16] 183
4-2-9. MDT [15:8] 183
4-2-10. Valid MDT “y” Field Values 183
4-2-11. CRC [7:1] 184

4-3. CSD register 184
4-3-1. CSD Fields 184
4-3-2. CSD_STRUCTURE [127:126] - CSD register structure 185
4-3-3. SPEC_VERS [125:122] - System specification version 186
4-3-4. TAAC [119:112] - TAAC access-time definition 186
4-3-5. NSAC [111:104] 186
4-3-6. TRAN_SPEED [103:96] - Maximum bus clock frequency definition 186
4-3-7. CCC [95:84] - Supported Card command classes 186
4-3-8. READ_BL_LEN [83:80] - Data block length 187
4-3-9. READ_BL_PARTIAL [79] 187
4-3-10. WRITE_BLK_MISALIGN [78] 187
4-3-11. READ_BLK_MISALIGN [77] 187
4-3-12. DSR_IMP [76] - DSR implementation code table 188
4-3-13. C_SIZE [73:62] 188
4-3-14. VDD_R_CURR_MIN [61:59] and VDD_W_CURR_MIN [55:53] - VDD (min) current consumption 188
4-3-15. VDD_R_CURR_MAX [58:56] and VDD_W_CURR_MAX [52:50] - VDD (max) current consumption 188
4-3-16. C_SIZE_MULT [49:47] - Multiplier factor for Card size 189
4-3-17. ERASE_GRP_SIZE [46:42] 189
4-3-18. ERASE_GRP_MULT [41:37] 189
4-3-19. WP_GRP_SIZE [36:32] 189
4-3-20. WP_GRP_ENABLE [31] 189
4-3-21. DEFAULT_ECC [30:29] 189
4-3-22. R2W_FACTOR [28:26] 189
4-3-23. R2W_FACTOR 189
4-3-24. WRITE_BL_LEN [25:22] 190
4-3-25. WRITE_BL_PARTIAL[21] 190
4-3-26. CONTENT_PROT_APP [16] 190
4-3-27. FILE_FORMAT_GRP [15] 190
4-3-28. COPY [14] 190
4-3-29. PERM_WRITE_PROTECT [13] 190
4-3-30. TMP_WRITE_PROTECT [12] 191
4-3-31. FILE_FORMAT [11:10] - File formats 191
4-3-32. ECC [9:8] - ECC type 191
4-3-33. CRC [7:1] 191
4-3-34. CSD field command classes 191
4-3-35. CSD retrieval and host adjustment 193
4-3-36. Card Payload block length and ECC types handling 193

4-4. EXT_CSD register 193
4-4-1. EXT_CSD 193
4-4-2. EXT_SECURITY_ERR [505] - EXT_SECURITY_ERR byte description 198
4-4-3. S_CMD_SET [504] - Card-supported command sets 199
4-4-4. HPI_FEATURES [503] 199
4-4-5. BKOPS_SUPPORT [502] - Background operations support 199
4-4-6. MAX_PACKED_READS [501] 200
4-4-7. MAX_PACKED_WRITES [500] 200
4-4-8. DATA_TAG_SUPPORT [499] 200
4-4-9. TAG_UNIT_SIZE [498] 200
4-4-10. TAG_RES_SIZE [497] 200
4-4-11. CONTEXT_CAPABILITIES [496] - Context Management Context Capabilities 200
4-4-12. LARGE_UNIT_SIZE_M1 [495] 200
4-4-13. EXT_SUPPORT [494] - EXT_CSD Register Support 201
4-4-14. SUPPORTED_MODES [493] - SUPPORTED_MODES 201
4-4-15. FFU_FEATURES [492] 201
4-4-16. OPERATION_CODES_TIMEOUT [491] - MODE_OPERATION_CODES timeout definition 201
4-4-17. FFU_ARG [490-487] 201
4-4-18. BARRIER_SUPPORT [486] 202
4-4-19. CMDQ_SUPPORT [308] 202
4-4-20. CMDQ_DEPTH [307] 202
4-4-21. NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED [305-302] 202
4-4-22. VENDOR_PROPRIETARY_HEALTH_REPORT [301-270] 202
4-4-23. CARD_LIFE_TIME_EST_TYP_B [269] - Card life time estimation type B value 202
4-4-24. CARD_LIFE_TIME_EST_TYP_A [268] - Card life time estimation type A value 203
4-4-25. PRE_EOL_INFO [267] - Pre EOL info value 203
4-4-26. OPTIMAL_READ_SIZE [266] - Optimal read size value 204
4-4-27. OPTIMAL_WRITE_SIZE [265] - Optimal write size value 204
4-4-28. OPTIMAL_TRIM_UNIT_SIZE [264] - Optimal trim unit size value 204
4-4-29. CARD_VERSION [263-262] 204
4-4-30. FIRMWARE_VERSION [261-254] 204
4-4-31. CACHE_SIZE [252:249] 205
4-4-32. GENERIC_CMD6_TIME [248] - Generic Switch Timeout Definition 205
4-4-33. Power off long switch timeout definition 205
4-4-34. BKOPS_STATUS [246] - Background operations status 205
4-4-35. CORRECTLY_PRG_SECTORS_NUM [245:242] - Correctly programmed sectors number 206
4-4-36. INI_TIMEOUT_AP [241] - Initialization Time out value 206
4-4-37. CACHE_FLUSH_POLICY [240] - Cache Flushing Policy 206
4-4-38. TRIM_MULT [232] - TRIM/DISCARD Time out value 206
4-4-39. SEC_FEATURE_SUPPORT [231] - SEC Feature Support 207
4-4-40. SEC_ERASE_MULT [230] - Secure Erase time-out value 207
4-4-41. SEC_TRIM_MULT [229] - Secure Erase Timeout value 208
4-4-42. BOOT_INFO [228] - Boot information 208
4-4-43. BOOT_SIZE_MULT [226] - Boot partition size 209
4-4-44. ACC_SIZE [225] 209
4-4-44-1. Superpage size 209
4-4-45. HC_ERASE_GRP_SIZE [224] - Erase-unit size 209
4-4-45-1. Erase unit size selection flow 210
4-4-46. ERASE_TIMEOUT_MULT [223] - Erase timeout values 211
4-4-47. REL_WR_SEC_C [222] - Reliable write sector count 212
4-4-48. HC_WP_GRP_SIZE [221] - Write protect group size 212
4-4-49. S_C_VCC[220] and S_C_VCCQ[219] - S_C_VCC, S_C_VCCQ Sleep Current 212
4-4-50. PRODUCTION_STATE_AWARENESS_TIMEOUT [218] - Production State Awareness timeout definition 213
4-4-51. S_A_TIMEOUT [217] - Sleep/awake timeout values 213
4-4-52. SLEEP_NOTIFICATION_TIME [216] - Sleep Notification timeout values 213
4-4-53. SEC_COUNT [215:212] 214
4-4-54. SECURE_WP_INFO[211] 214
4-4-55. MIN_PERF_a_b_ff [210/:205] and MIN_PERF_DDR_a_b_ff [235:234] - R/W access performance values 214
4-4-56. PWR_CL_ff_vvv [203:200] , PWR_CL_ff_vvv[237:236] , PWR_CL_DDR_ff_vvv [239:238]
and PWR_CL_DDR_ff_vvv[253] - Power classes 215
4-4-57. PARTITION_SWITCH_TIME [199] - Partition switch timeout definition 216
4-4-58. OUT_OF_INTERRUPT_TIME [198] - Out-of-interrupt timeout definition 217
4-4-59. DRIVER_STRENGTH [197] - Supported Driver Strengths 217
4-4-60. CARD_TYPE [196] - Card types 217
4-4-61. CSD_STRUCTURE [194] - CSD register structure 218
4-4-62. EXT_CSD_REV [192] - EXT_CSD revisions 218
4-4-63. CMD_SET [191] 218
4-4-64. CMD_SET_REV [189] - Standard MMC command set revisions 219
4-4-65. POWER_CLASS [187] - Power class codes 219
4-4-66. HS_TIMING [185] - HS_TIMING (timing and driver strength) 219
4-4-66-1. HS_TIMING Interface values 219
4-4-67. STROBE_SUPPORT [184] 220
4-4-68. BUS_WIDTH [183] 220
4-4-68-1. Bus Mode Selection 220
4-4-69. ERASEND_MEM_CONT [181] - Erased memory content values 220
4-4-70. PARTITION_CONFIG (before BOOT_CONFIG) [179] — Boot configuration bytes 221
4-4-71. BOOT_CONFIG_PROT[178] — Boot configuration protection 221
4-4-72. BOOT_BUS_CONDITIONS [177] - Boot bus configuration 222
4-4-73. Bus Width and Timing Mode Transition 223
4-4-74. ERASE_GROUP_DEF [175] 223
4-4-75. BOOT_WP_STATUS [174] 223
4-4-76. BOOT_WP [173] — BOOT area Partitions write protection 224
4-4-77. USER_WP [171] — User area write protection 225
4-4-78. FW_CONFIG [169] — FW Update Disable 226
4-4-79. RPMB_SIZE_MULT [168] — RPMB Partition Size 226
4-4-80. WR_REL_SET [167] — Write reliability setting 226
4-4-81. WR_REL_PARAM [166] — Write reliability parameter register 227
4-4-82. SANITIZE_START[165] 228
4-4-83. BKOPS_START [164] 228
4-4-84. BKOPS_EN [163] — Background operations enable 228
4-4-85. RST_n_FUNCTION [162] — H/W reset function 228
4-4-86. HPI_MGMT [161] — HPI management 229
4-4-87. PARTITIONING_SUPPORT [160] — Partitioning Support 229
4-4-88. MAX_ENH_SIZE_MULT [159:157] — Max. Enhanced Area Size 229
4-4-89. PARTITIONS_ATTRIBUTE [156] — Partitions Attribute 229
4-4-90. PARTITION_SETTING_COMPLETED [155] — Partition Setting 230
4-4-91. GP_SIZE_MULT_GP0 - GP_SIZE_MULT_GP3 [154:143] — General Purpose Partition Size 230
4-4-92. ENH_SIZE_MULT [142:140] — Enhanced User Data Area Size 231
4-4-93. ENH_START_ADDR [139:136] — Enhanced User Data Start Address 231
4-4-94. SEC_BAD_BLK_MGMNT [134] — Secure Bad Block management 231
4-4-95. PRODUCTION_STATE_AWARENESS [133] — PRODUCTION_STATE_AWARENESS states 232
4-4-96. TCASE_SUPPORT [132] 232
4-4-97. PERIODIC_WAKEUP [131] — PERIODIC_WAKEUP 232
4-4-98. PROGRAM_CID_CSD_DDR_SUPPORT [130] — CMD26 and CMD27 in DDR mode Support 233
4-4-99. VENDOR_SPECIFIC_FIELD [127:64] 233
4-4-100. NATIVE_SECTOR_SIZE [63] 233
4-4-101. USE_NATIVE_SECTOR [62] 233
4-4-102. DATA_SECTOR_SIZE [61] 234
4-4-103. INI_TIMEOUT_EMU [60] — Initialization Time out value 234
4-4-104. CLASS_6_CTRL[59] — Class 6 usage 234
4-4-105. DYNCAP_NEEDEDED [58] 234
4-4-106. EXCEPTION_EVENTS_CTRL [57:56] 234
4-4-106-1. EXCEPTION_EVENTS_CTRL[56] 234
4-4-106-2. EXCEPTION_EVENTS_CTRL[57] 234
4-4-107. EXCEPTION_EVENTS_STATUS [55:54] 235
4-4-107-1. EXCEPTION_EVENTS_STATUS[54] 235
4-4-107-2. EXCEPTION_EVENTS_STATUS[55] 235
4-4-108. EXT_PARTITIONS_ATTRIBUTE [53:52] 235
4-4-108-1. First Byte EXT_PARTITIONS_ATTRIBUTE[52] 235
4-4-108-2. Second Byte EXT_PARTITIONS_ATTRIBUTE[53] 235
4-4-109. CONTEXT_CONF [51:37] — CONTEXT_CONF configuration format 236
4-4-110. PACKED_COMMAND_STATUS [36] — Packed Command Status Register 236
4-4-111. PACKED_FAILURE_INDEX [35] 236
4-4-112. POWER_OFF_NOTIFICATION [34] — Valid POWER_OFF_NOTIFICATION values 237
4-4-113. CACHE_CTRL [33] — CACHE ENABLE 237
4-4-114. FLUSH_CACHE [32] — FLUSH CACHE 237
4-4-115. BARRIER_CTRL [31] — BARRIER_CTRL 238
4-4-116. MODE_CONFIG [30] — Valid MODE_CONFIG values 238
4-4-117. MODE_OPERATION_CODES [29] — Valid MODE_OPERATION_CODES values 238
4-4-118. FFU_STATUS [26] — FFU Status codes 238
4-4-119. PRE_LOADING_DATA_SIZE [25-22] 238
4-4-120. 118 MAX_PRE_LOADING_DATA_SIZE [21-18] 239
4-4-121. PRODUCT_STATE_AWARENESS_ENABLEMENT [17] — Production State Awareness Enablement 239
4-4-122. SECURE_REMOVAL_TYPE [16] — Secure Removal Type 240
4-4-123. CMDQ_MODE_EN [15] — Command Queue Mode Enable 240

4-5. RCA register 240

4-6. DSR register 241

4-7. QSR 241

4-8. Authenticated Card Configuration Area 241
4-8-1. Authenticated Card Configuration Area[1] : SECURE_WP_MODE_ENABLE 241
4-8-2. Authenticated Card Configuration Area[2] : SECURE _WP_MODE_CONFIG 241

5. Commands 243
5-1. Command types 243
5-1-1. Command format 243

5-2. Command classes 243
5-2-1. Supported Card command classes (0–56) 243

5-3. Detailed command description 244
5-3-1. Basic commands (class 0 and class 1) 244
5-3-2. Block-oriented read commands (class 2) 245
5-3-3. Class 3 commands 246
5-3-4. Block-oriented write commands (class 4) 246
5-3-5. Block-oriented write protection commands (class 6) 247
5-3-6. Erase commands (class 5) 248
5-3-7. I/O mode commands (class 9) 249
5-3-8. Lock Card commands (class 7) 249
5-3-9. Application-specific commands (class 8) 249
5-3-10. Security Protocols (class 10) 250
5-3-11. Command Queue (Class 11) 250

5-4. Card state transition table 250

5-5. eMMC macro commands 254
5-5-1. Macro commands 254
5-5-2. Legend for command-sequence flow charts 254
5-5-3. SEND_OP_COND command flow chart 255
5-5-4. CIM_SINGLE_CARD_ACQ 256
5-5-5. CIM_SETUP_CARD 257
5-5-6. CIM_READ_BLOCK 258
5-5-7. CIM_READ_MBLOCK 258
5-5-8. CIM_WRITE_BLOCK 259
5-5-9. CIM_WRITE_MBLOCK 259
5-5-10. CIM_ERASE_GROUP 260
5-5-11. CIM_TRIM 260
5-5-12. CIM_US_PWR_WP 261
5-5-13. CIM_US_PERM_WP 262

6. Responses 264
6-1. R1(normal response command) response 264
6-1-1. R1b 264
6-2. R2(CID, CSD register) response 264
6-3. R3(OCR register) response 264
6-4. R4 (Fast I/O) response 264
6-5. R5 (Interruption request) response 265

6-6. Card status 265
6-6-1. Card status table 266
6-6-2. Card Status field/command - cross reference 268
6-6-3. Response 1 Status Bit Valid 268

7. (Normative) Host Controller Interface for Command Queuing 270
7-1. Introduction 270
7-1-1. Background 270
7-1-2. Overview and Scope 270
7-1-3. Feature Summary 270

7-2. Architecture Overview 270
7-2-1. Proposed Host System Architecture, with CQE 270
7-2-2. Task Issuance: Task Descriptor List / Doorbell Register 271
7-2-3. Command Queuing HCI General Architecture 271
7-2-4. Task Processing by Host Hardware 272
7-2-5. Task Selection and Execution 272
7-2-6. Task Completion: Interrupts and Interrupt Coalescing 272
7-2-7. Direct Command (DCMD) Submission 272
7-2-8. Queue-Barrier (QBR) Tasks 273
7-2-9. Halt Feature 273
7-2-10. Error Detection and Recovery 274
7-2-10-1. Handling of Error Conditions in CQE 274

7-3. CQE Data Structures 274
7-3-1. Task Descriptor for Data Transfer Tasks 274
7-3-1-1. Task Descriptor Structure; Lower 64 bits (Data Transfer tasks) 275
7-3-1-2. Task Descriptor Structure; Upper 64 bits 275
7-3-1-3. Task Descriptor for Data Transfer Tasks - Task Descriptor Fields 275

7-4. Transfer Descriptors 275
7-4-1. Transfer Descriptor Structure (32-bit addressing) 276
7-4-2. Transfer Descriptor Structure (64-bit addressing) 276
7-4-3. Transfer Descriptor Fields 276

7-5. Task Descriptor for Direct-Command (DCMD) Tasks 276
7-5-1. Task Descriptor Structure: Lower 64 bits (for DCMD tasks) 277
7-5-2. Task Descriptor Fields (for DCMD tasks) 277
7-5-3. Task Descriptor for Queue-Barrier Task (QBR) 278
7-5-4. Task List 278

7-6. CQE Registers 278
7-6-1. Register Map— CQE Register Map 278
7-6-2. CQBASE+00h: CQVER – Command Queuing Version 279
7-6-3. 3CQBASE+04h: CQCAP – Command Queuing Capabilities 279
7-6-4. CQBASE+08h: CQCFG – Command Queuing Configuration 280
7-6-5. CQBASE+0Ch: CQCTL – Command Queuing Control 280
7-6-6. CQBASE+10h: CQIS – Command Queuing Interrupt Status 281
7-6-7. CQBASE+14h: CQISTE – Command Queuing Interrupt Status Enable 281
7-6-8. CQBASE+18h: CQISGE – Command Queuing Interrupt Signal Enable 282
7-6-9. CQBASE+1Ch: CQIC – Interrupt Coalescing 282
7-6-10. CQBASE+20h: CQTDLBA – Command Queuing Task Descriptor List Base Address 283
7-6-11. CQBASE+24h: CQTDLBAU – Command Queuing Task Descriptor List Base Address 284
7-6-12. CQBASE+28h: CQTDBR – Command Queuing Task Doorbell 284
7-6-13. CQBASE+2Ch: CQTCN – Task Completion Notification 284
7-6-14. CQBASE+30h: CQDQS – Card Queue Status 285
7-6-15. CQBASE+34h: CQDPT – Card Pending Tasks 285
7-6-16. CQBASE+38h: CQTCLR – Task Clear 285
7-6-17. CQBASE+40h: CQSSC1 – Send Status Configuration 1 286
7-6-18. CQBASE+44h: CQSSC2 – Send Status Configuration 2 286
7-6-19. CQBASE+48h: CQCRDCT – Command Response for Direct-Command Task 286
7-6-20. CQBASE+50h: CQRMEM – Response Mode Error Mask 287
7-6-21. CQBASE+54h: CQTERRI - Task Error Information 287
7-6-22. CQBASE+58h: CQCRI – Command Response Index 288
7-6-23. CQBASE+5Ch: CQCRA – Command Response Argument 288

7-7. Command Queuing Interrupt in eMMC Host Controller 288
7-7-1. Normal Interrupt Status Register (Offset 030h) 288
7-7-2. Normal Interrupt Status Enable Register (Offset 034h) 288
7-7-3. Normal Interrupt Signal Enable Register (Offset 038h) 289

7-8. Command Queue: Command Flows (Informative) 289
7-8-1. Queuing a Transaction (CMD44+CMD45) 289
7-8-1-1. Queuing a transaction 289
7-8-2. Checking the Queue Status (SEND_STATUS - CMD13) 289
7-8-3. Execution of a Queued Task (CMD46/CMD47) 289
7-8-3-1. Execution of a queued task 290

7-9. Theory of Operation (Informative) 290
7-9-1. Command Queuing Initialization Sequence 290
7-9-2. Task Issuance Sequence 290
7-9-3. Task Queuing Sequence 291
7-9-4. Task Completion Sequence 291
7-9-5. Task Execution and Completion Sequence 291
7-9-6. Task Discard Sequence (inc. Halting CQE) 292
7-9-7. Task Discard and Clear Sequence Diagram 292

7-10. Error Detect and Recovery 293

8. eMMC 主要单词说明 295

도서 정보

书籍简介

这本书是为使读者更容易理解现有的eMMC产品规格书而设计的。 公司内的工程师至少需要3个月到6个月才能理解现有的spec。 其理由如下:第一,由于不是各国母语,而是官方语言——英语,所以重新翻译和理解外语需要很长时间,而且由于个别翻译能力的差异,也没有保证所有人都能正确翻译其意义。 由此导致工程师之间产生多种理解错误、沟通错误。 第二,像学生一样,在只能学习的条件下工作的工程师在世界上任何公司都不存在。 整天忙于工作,在空闲的时间或工作过程中,只学习相关部分,因此,学习和理解整体内容的工程师很难找出事实。 这么看来,时间过的内容都理解能力不强,缺乏的知识,注意的人得到严厉的目光往往发生。 第三种是spec,其排列方式是依次、按顺序排列,为了理解现在所看到的spec,会突然向后移动,反复前行。 由此导致可读性下降,理解程度降低的问题。
公司以高薪聘请工程师,如果所有工程师理解产品资历至少需要半年时间,那么公司支付的费用浪费就相当于平均年薪和工程师数量的乘以。 不必要的开发费用浪费及开发时间增加,会给公司带来其他负担。
为了解决这些问题,本书将eMMC的标准文凭翻译成各国的母语,按顺序排列结构排列方式,以使看基本文凭时能更快、更容易理解为目标。 (但是,有画的部分是用多种语言制作,为了回收利用,所以直接使用了英语,敬请谅解。)

书的排列方式采用三种方式。
第一个方式按概要 → HW → State diagram -> Register -> CMD顺序排列。 用人来比喻,在说明身体构成部分后,如果说明大脑如何控制身体各部分,理解起来就会更快一些。
第二种是有相关关系的内容,放在同一个地方,在书里不到处走动,在一个地方都可以看到。
第三,除此之外,现有的spec构成的配置不会发生大的改变。 在制作spec的时候也是经过很多考虑之后才制作的,所以很多部分已经排得很整齐。

通过这本书,希望公司开发eMMC的工程师能帮助他们尽快学习工作时间不足的spec;希望想就职半导体相关公司的就业准备生们能通过在存储器半导体上最基础、最根本的eMMC学习的公司。
本书参照JESD84-B51A制作。