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분야기타 > 과학/IT
작가김영민
출판형태종이책
페이지수 319 Pages
인쇄컬러표지-컬러, 내지-흑백
판형 A4
출판사부크크
ISBN979-11-372-1578-8
출판일2020.08.25
총 상품 금액 30,000

저자 소개

저자 김영민

전 삼성전자 반도체 사업부 상품기획팀 (eMMC 담당)
전 하이닉스 Storage 개발팀 (eMMC 개발 담당)

Homepage http://easyrun.co.kr

번역자 소개 (번역서인 경우 입력해주세요.)

목차

목차

1. eMMC 개요 20
1-1. eMMC System 개요 20
1-2. System 특징 20
1-3. System 동작 전압 구성 21
1-4. 기본 동작 전압의 Timing 설명 21
1-5. Bus Protocol 22
1-6. Register 종류 23
1-6-1. CID Fields : 16 bytes 23
1-6-2. RCA register : 2 bytes 24
1-6-3. DSR register content : 2 bytes 24
1-6-4. CSD Fields 24
1-6-5. OCR register 25
1-6-6. EXT_CSD fields : 512 bytes 26
1-7. 동작 명령어들 31
1-8. 주요 State diagram 35
1-8-1. eMMC state diagram (boot mode) 35
1-8-2. eMMC state diagram (Card identification mode) 35
1-8-3. eMMC state diagram (data transfer mode) 36
1-8-4. eMMC state transition diagram, interrupt mode 37
1-9. Multiple-block의 CMD, Data 간의 기본 동작 37
1-9-1. Multiple-block read operation 37
1-9-2. Multiple-block write operation 37
1-9-3. No ‘response’ and ‘no data’ operations 38

2. eMMC Hardware 39
2-1. Power supply 39
2-1-1. eMMC eMMC internal power diagram 39
2-1-2. e2MMC internal power diagram 39

2-2. High Speed System Block diagram 40
2-2-1. HS200 System Block diagram 40
2-2-2. HS400 System Block diagram 41

2-3. eMMC Power-up 41
2-3-1. eMMC voltage combinations 41
2-3-2. Power supply Voltages 42
2-3-3. Power-up 42
2-3-4. Power-up diagram 42
2-3-5. eMMC power-up diagram 44
2-3-6. eMMC power-up guidelines 44
2-3-7. eMMC power cycle 45

2-4. eMMC bus 46
2-4-1. Bus circuitry diagram 46
2-4-2. Bus signal levels 47
2-4-3. Programmable Card output driver 48
2-4-4. DSR register content 48
2-4-5. eMMC bus driver 48
2-4-6. Bus signal line load 49
2-4-7. Capacitance and Resistors 50
2-4-8. Bus general operating conditions 50
2-4-9. High-speed eMMC bus functions 51
2-4-9-1. Bus initialization 51
2-4-10. Bus Operating Conditions for HS200 and HS400 52
2-4-11. Card Output Driver Requirements for HS200 and HS400 52
2-4-11-1. Driver Types Definition 52
2-4-11-2. I/O driver strength types 52
2-4-12. Driver Type-0 AC Characteristics 53
2-4-12-1. Driver Type-0 AC Characteristics 53
2-4-12-2. Driver Type-0 Test Circuit 53
2-4-12-3. Outputs test circuit for rise/fall time measurement 53
2-4-13. Driver Type Selection 54

2-5. Bus Speed Modes 54
2-5-1. eMMC에서 제공하는 다양한 Bus Speed 모드 54
2-5-2. High Speed mode 특징 54
2-5-3. 데이터 Bus width 변경 55
2-5-4. XNOR values 55
2-5-5. Switching to high-speed mode 56
2-5-6. Speed class definition 56
2-5-7. Measurement of the performance 57

2-6. Block operation 57
2-6-1. Multiple-block operation 57
2-6-1-1. Multiple-block read operation 57
2-6-1-2. Multiple-block write operation 58
2-6-1-3. No ‘response’ and ‘no data’ operations 58

2-7. Token format 개념 58
2-7-1. Command token format : 명령 토큰 형식 59
2-7-2. Response token format 59
2-7-3. SDR (Single Data Rate)용 Data packet format 59
2-7-3-1. 1 Bit bus (only DAT0 사용) 59
2-7-3-2. 4 Bits bus (DAT0 ~ DATA3 사용) 60
2-7-3-3. 8 Bits bus (DAT0 ~ DAT7 사용) 60
2-7-4. DDR (Double Data Rate)용 Data packet format 60
2-7-4-1. 4 Bit bus DDR (DAT0 ~ DAT3 사용) 61
2-7-4-2. 8 Bit bus DDR (DAT0 ~ DAT7 사용) 61
2-7-4-3. 8 Bit bus DDR for HS400 output (DAT7 ~ DAT0 사용) 62
2-7-5. DDR52용 CRC status token 63
2-7-5-1. Positive CRC status token (‘010’) 또는 Boot 인지 패턴일 경우 63
2-7-5-2. Negative CRC status token (‘101’)일 경우 63
2-7-5-3. HS400용 status CRC token 64
2-7-5-4. Positive CRC status token (‘010’)일 경우 64
2-7-6-5. Negative CRC status token (‘101’)일 경우 64
2-7-6. Error conditions 64
2-7-6-1. CRC and illegal command 64

2-8. Timings 64
2-8-1. Clock control 65
2-8-2. Command and response 65
2-8-2-1. Identification timing (Card identification mode) 65
2-8-2-2. SET_RCA timing (Card identification mode) 66
2-8-2-3. Command response timing (data transfer mode) 66
2-8-2-4. R1b response timing 66
2-8-2-5. R1b Timing 66
2-8-2-6. Timing response end to next command start (data transfer mode) 66
2-8-2-7. Timing of command sequences (all modes) 67
2-8-3. Data read 67
2-8-3-1. Single-block read timing 67
2-8-3-2. Multiple-block read timing 68
2-8-3-3. Stop command timing (CMD12, data transfer mode) 68
2-8-3-4. Read ahead in multiple block read operation 68
2-8-3-5. Data Strobe Read Timing 68
2-8-3-6. HS400 Read Timing with data block size of 512 bytes 68
2-8-3-7. Read Block Gap 69
2-8-3-8. Clock Stop Timing at Block Gap in Read Operation 69
2-8-4. Data write 69
2-8-4-1. Block write command timing 70
2-8-4-2. Multiple-block write timing 70
2-8-4-3. HS400 Write Timing 71
2-8-4-4. HS400 Write Timing with data block size of 512 bytes 71
2-8-4-5. NCRC timing 71
2-8-4-6. BUSY Signal after CRC Status Response 71
2-8-5. Stop transmission 72
2-8-5-1. Stop transmission during data transfer from the host 72
2-8-5-2. Stop transmission during CRC status transfer from the Card 72
2-8-5-3. Stop transmission after last data block; Card is busy programming 73
2-8-5-4. Reselecting a Busy Card 73
2-8-5-5. Stop transmission after last data block; Card becomes busy 73
2-8-5-6. Stop transmission timing 74
2-8-5-7. Stop transmission just before CRC status transfer from the Card 74
2-8-5-8. Stop transmission during CRC status transfer from the Card - 1 74
2-8-5-9. Stop transmission during CRC status transfer from the Card - 2 74
2-8-6. CMD12 Timing Modification 75
2-8-6-1. CMD12 Timing Modification in Write Operation 75
2-8-6-2. Border Timing of CMD12 in Write Operation 75
2-8-6-3. CMD12 Timing Modification in Read Operation 75
2-8-6-4. Border Timing of CMD12 in Read Operation 76
2-8-7. Enhanced Strobe in HS400 Mode 76
2-8-7-1. Enhanced Strobe signals for CMD Response and Data Out (Read operation) 76
2-8-7-2. Enhanced Strobe signals for CMD Response and CRC Response (Write operation) 76
2-8-7-3. HS400 mode change with Enhanced Strobe 77
2-8-8. Bus test procedure timing 77
2-8-8-1. Bus test procedure timing 77
2-8-9. Boot operation 77
2-8-9-1. Boot operation, termination between consecutive data blocks 77
2-8-9-2. Boot operation, termination during transfer 78
2-8-9-3. Bus mode change timing (push-pull to open-drain) 78
2-8-10. Alternative boot operation 78
2-8-10—1. Alternative boot operation, termination between consecutive data blocks 78
2-8-10-2. Alternative boot operation, termination during transfer 79

2-9. High speed Timing Values 79
2-9-1. Timing Parameters 79
2-9-2. Timing changes in HS200 and HS400 mode 80
2-9-2-1. Timing values 80
2-9-2-2. Timing Parameters for HS200 and HS400 mode 80
2-9-2-3. Timing diagram : data input / output in single data rate mode 80
2-9-3. Card interface timings 81
2-9-3-1. High-speed Card interface timing 81
2-9-4. Bus Timing Specification in HS200 mode 81
2-9-4-1. HS200 Clock Timing 81
2-9-4-2. HS200 Clock signal timing 81
2-9-4-3. HS200 Clock signal timing table 82
2-9-4-4. HS200 Card Input Timing 82
2-9-4-5. HS200 Card input timing table 82
2-9-4-6. HS200 Card Output Timing 83
2-9-4-7. HS200 Card output timing table 83
2-9-4-8. ∆TPH consideration 84
2-9-5. Bus Timing Specification in HS400 mode 84
2-9-5-1. HS400 Card Input Timing 84
2-9-5-2. HS400 Card input timing table 85
2-9-5-3. HS400 Card Output Timing 85
2-9-5-4. HS400 Card output timing table 85
2-9-5-5. HS400 Capacitance and Resistors 86
2-9-5-6. HS400 Card Command Output Timing 86
2-9-5-7. HS400 CMD Response timing 86
2-9-5-8. HS400 CMD Response timing table 87
2-9-5-9. HS400 reference load 87

2-10. Host Forward/Backward-compatible Card interface timing 88
2-10-1. Forward-compatible host interface timing 88
2-10-2. Backward-compatible Card interface timing 89
2-10-3. Timing diagram : data input / output in dual data rate mode 89
2-10-4. Bus timing for DAT signals during 2x data rate operation 90
2-10-5. High-speed Dual data rate interface timings 90
2-10-6. High-speed Card interface timing 91
2-10-7. Backward-compatible Card interface timing 92

2-11. AC Overshoot/Undershoot Specification 93
2-11-1. Overshoot/Undershoot definition 93

2-12. Partition management 93
2-12-1. Command restrictions 95
2-12-2. Boot partition 95
2-12-2-1. BOOT_SIZE_MULT [226] - EXT_CSD : Boot partition size 96
2-12-2-2. RPMB_SIZE_MULT [168] - EXT_CSD : RPMB Partition Size 96
2-12-3. Handling write protection for each boot area individually 97
2-12-4. Extended Partitions Attribute 97
2-12-5. Configure partitions 98
2-12-6. Flow chart for General Purpose Partitions & Enhanced User Data Area parameter setting 99
2-12-7. Memory array partitioning 101

2-13. Time-out conditions 102

2-14. Error protection 103
2-14-1. Error correction codes (ECC) 103
2-14-2. Cyclic redundancy codes (CRC) 104
2-14-3. CRC7 104
2-14-4. CRC7 generator/checker 104
2-14-5. CRC16 104
2-14-6. CRC16 generator/checker 105

2-15. Temperature Conditions 105
2-15-1. Temperature Conditions per Power Classes (Tcase controlled) 105
2-15-2. Heat Removal - Nomenclatures 106
2-15-3. Package Case Temp (Tc) per current consumption 106

2-16. eMMC standard compliance 107
2-16-1. eMMC host requirements for Card classes 107
2-16-2. New Features List for Card type 108

3. eMMC functional description 110
3-1. Operation mode, Card state, CMD line mode의 상관 관계 110
3-1-1. Open-drain mode bus signal level 110
3-1-2. Push-pull mode bus signal level 111
3-1-3. Push-pull signal level - high-voltage 111
3-1-4. Push-pull signal level - 1.70 V -1.95 V VCCQ voltage Range 111
3-1-5. Push-pull signal level - 1.1 V-1.3 V VCCQ range 111

3-2. Boot mode 111
3-2-1. Card reset to Pre-idle state 111
3-2-2. WP condition transition due to H/W reset assertion 112
3-2-2-1. RST_n signal at the power up period 112
3-2-2-2. H/W reset timing parameters 113
3-2-2-3. H/W reset waveform 113
3-2-2-4. Noise filtering timing for H/W Reset 113
3-2-3. Boot operation mode 114
3-2-3-1. Boot mode timing cycle 114
3-2-4. Alternative boot operation 115
3-2-4-1. Alternative boot mode timing cycle 116
3-2-5. Clarification of RESET_BOOT_BUS_CONDITIONS behavior when CMD0 is issued in IDLE 116
3-2-6. Access to boot partition 117
3-2-7. Boot bus width and data access configuration 118
3-2-8. Boot Partition Write Protection 118
3-2-9. Setting EXT CSD BOOT_WP [173] 118

3-3. Card identification mode 119
3-3-1. Card reset 119
3-3-2. Card identification mode state diagram 120
3-3-3. Access mode validation (higher than 2GB of densities) 120
3-3-4. From busy to ready 121
3-3-5. Card identification process 121

3-4. Interrupt mode 122
3-4-1. eMMC state transition diagram, interrupt mode 122

3-5. Data transfer mode 123
3-5-1. data transfer mode state diagram 123
3-5-2. Command sets and extended settings 126
3-5-3. EXT_CSD access mode 126
3-5-4. High speed modes selection 126
3-5-4-1. “High speed” mode selection 127
3-5-4-2. “HS200” timing mode selection 127
3-5-4-3. HS200 Selection flow diagram 128
3-5-4-4. “HS400” timing mode selection 128
3-5-4-5. HS400 Selection flow diagram 129
3-5-4-6. HS400 (Enhanced Strobe) Slection flow diagram 131
3-5-5. Power class selection 131
3-5-6. Bus testing procedure 131
3-5-6-1. Bus testing pattern 132
3-5-6-2. 1 bit bus testing pattern 132
3-5-6-3. 4 bit bus testing pattern 132
3-5-6-4. 8 bit bus testing pattern 133
3-5-6-5. Bus testing for eight data lines 133
3-5-6-6. Bus testing for four data lines 134
3-5-6-7. Bus testing for one data line 134
3-5-7. Bus Sampling Tuning Concept 134
3-5-7-1. Sampling Tuning Sequence for HS200 134
3-5-7-2. Send Tuning Command 135
3-5-7-3. Tuning block pattern for 8 bit mode 135
3-5-7-4. Tuning block on DAT[7:0]/DAT[3:0] in 8 bit/4 bit bus width 136
3-5-8. Bus width selection 137
3-5-9. Data read 137
3-5-9-1. Block read 137
3-5-10. Data write 138
3-5-11. Block write 139
3-5-12. Erase 141
3-5-12-1. Erase command (CMD38) Valid arguments 142
3-5-13. TRIM 142
3-5-14. Sanitize 143
3-5-15. Discard 144
3-5-16. Secure Erase 144
3-5-16-1. Erase command (CMD38) Valid arguments 145
3-5-17. Secure Trim 145
3-5-18. Write protect management 147
3-5-18-1. Write Protection Hierarchy (when diable bits are clear) 148
3-5-18-2. Write Protection Types (when diable bits are clear) 148
3-5-19. Extended Security Protocols Pass Through Commands 148
3-5-19-1. PROTOCOL_RD - CMD53 149
3-5-19-2. PROTOCOL_WR - CMD54 149
3-5-19-3. Security Protocols (class 10) 149
3-5-19-4. Security Protocol Type 149
3-5-19-5. Security Protocol Information 150
3-5-19-6. Error handling 150
3-5-20. Production State Awareness 150
3-5-20-1. Manual Mode 151
3-5-20-2. Auto Mode 151
3-5-20-3. Recommended Soldering procedure 151
3-5-21. Field Firmware Update 152
3-5-21-1. FFU flow 153
3-5-22. Card lock/unlock operation 154
3-5-22-1. Lock Card data structure 155
3-5-22-2. Setting the password 155
3-5-22-3. Reset the password 156
3-5-22-4. Locking the Card 157
3-5-22-5. Description of method for storing passwords on the Card 158
3-5-22-6. Handling of passwords 158
3-5-22-7. Changing the password 159
3-5-22-8. Removal of the password 159
3-5-22-9. Forcing erase 159
3-5-23. Application-specific commands 160
3-5-23-1. Sleep (CMD5) 160
3-5-24. Replay Protected Memory Block 161
3-5-24-1. Data Frame Files for RPMB 161
3-5-24-2. RPMB Request/Response Message Types 162
3-5-24-3. RPMB Operation Results data structure 162
3-5-24-4. RPMB Operation Results 163
3-5-24-5. Memory Map of the Replay Protected Memory Block 164
3-5-24-6. Message Authentication Code Calculation 164
3-5-24-7. MAC Example 164
3-5-24-8. Accesses to the Replay Protected Memory Block 165
3-5-24-9.. Programming of the Authentication Key 165
3-5-24-10. Authentication Key Data Packet 165
3-5-24-11. Result Register Read Request Packet 166
3-5-24-12. Response for Key Programming Result Request 166
3-5-24-13. Reading of the Counter Value 166
3-5-24-14. Counter Read Request Packet 167
3-5-24-15. Counter Value Response 167
3-5-24-16. Authenticated Data Write 167
3-5-24-17. Program Data Packet 168
3-5-24-18. Result Register Read Request Packet 168
3-5-24-19. Response for Data Programming Result Request 169
3-5-24-20. Authenticated Data Read 169
3-5-24-21. Data Read Request Initiation Packet 169
3-5-24-22. Read Data Packet 169
3-5-24-23. Authenticated Card Configuration Write 170
3-5-24-24. Authenticated Card Configuration Write packet 170
3-5-24-25. Response for Authenticated Card Configuration Write Request 171
3-5-24-26. Authenticated Card Configuration Read 171
3-5-24-27. Authenticated Card Configuration Read Initiation packet 171
3-5-24-28. Response for Authenticated Card Configuration Read 171
3-5-25. Dual Data Rate mode selection 172
3-5-26. Dual Data Rate mode operation 172
3-5-27. Background Operations 172
3-5-28. High Priority Interrupt (HPI) 173
3-5-28-1. Interruptible commands 174
3-5-28-2. HPI background and one of possible solutions 175
3-5-29. Context Management 175
3-5-29-1. Context configuration 176
3-5-29-2. Context direction 176
3-5-29-3. Large-Unit 177
3-5-29-4. Context Writing Interruption 177
3-5-29-5. Large-Unit Multipliers 178
3-5-30. Data Tag Mechanism 179
3-5-31. Packed Commands 179
3-5-31-1. Packed Command Header 180
3-5-31-2. Packed Command Structure 180
3-5-31-3. Packed Commands Error Handling 181
3-5-32. Exception Events 181
3-5-33. Cache 181
3-5-34. Features cross matrix 183
3-5-34-1. Features Cross Reference Table 183
3-5-35. Dynamic Capacity Management 184
3-5-36. Large sector size 185
3-5-36-1. eMMC internal sizes and related Units / Granularities 186
3-5-36-2. Disabling emulation mode 186
3-5-36-3. Native 4KB sector behavior 187
3-5-36-4. Admitted Data Sector Size, Address Mode and Reliable Write granularity 187
3-5-37. Real Time Clock Information 188
3-5-37-1. Real Time Clock Information Block Format 188
3-5-37-2. RTC_INFO_TYPE Field Description 188
3-5-37-3. Periodic Wake-up 189
3-5-38. Power Off Notification 189
3-5-39. Cache Enhancement Barrier 190
3-5-40. Cache Flushing Policy 191
3-5-41. Command Queuing 191
3-5-41-1. Overview 191
3-5-41-2. QUEUED_TASK_PARAMS - CMD44 192
3-5-41-3. QUEUED_TASK_ADDRESS - CMD45 192
3-5-41-4. EXECUTE_READ_TASK - CMD46 193
3-5-41-5. EXECUTE_WRITE_TASK - CMD47 193
3-5-41-6. CMDQ_TASK_MGMT - CMD48 193
3-5-41-7. Task Management op-codes 193
3-5-41-8. SEND_STATUS - CMD13 194
3-5-41-9. Error handling 194
3-5-41-10. Error handling for Command Queue 194
3-5-41-11. Supported Commands 194
3-5-41-12. Supported Commands for Command Queue 195
3-5-41-13. Secure Write Protect Mode 195
3-5-41-14. Card Configuration Area 195

4. Card Registers 196
4-1 OCR register 196
4-1-1. OCR register definitions 196

4-2. CID register 196
4-2-1. CID Fields 197
4-2-2. MID [127:120] 197
4-2-3. BIN [119:114] 197
4-2-4. CBX [113:112] 197
4-2-4-1. Card Types 197
4-2-6. PNM [103:56] 197
4-2-7. PRV [55:48] 197
4-2-8. PSN [47:16] 198
4-2-9. MDT [15:8] 198
4-2-10. Valid MDT “y” Field Values 198
4-2-11. CRC [7:1] 198

4-3. CSD register 198
4-3-1. CSD Fields 199
4-3-2. CSD_STRUCTURE [127:126] - CSD register structure 200
4-3-3. SPEC_VERS [125:122] - System specification version 200
4-3-4. TAAC [119:112] - TAAC access-time definition 200
4-3-5. NSAC [111:104] 201
4-3-6. TRAN_SPEED [103:96] - Maximum bus clock frequency definition 201
4-3-7. CCC [95:84] - Supported Card command classes 201
4-3-8. READ_BL_LEN [83:80] - Data block length 201
4-3-9. READ_BL_PARTIAL [79] 202
4-3-10. WRITE_BLK_MISALIGN [78] 202
4-3-11. READ_BLK_MISALIGN [77] 202
4-3-12. DSR_IMP [76] - DSR implementation code table 202
4-3-13. C_SIZE [73:62] 202
4-3-14. VDD_R_CURR_MIN [61:59] and VDD_W_CURR_MIN [55:53] - VDD (min) current consumption 203
4-3-15. VDD_R_CURR_MAX [58:56] and VDD_W_CURR_MAX [52:50] - VDD (max) current consumption 203
4-3-16. C_SIZE_MULT [49:47] - Multiplier factor for Card size 203
4-3-17. ERASE_GRP_SIZE [46:42] 204
4-3-18. ERASE_GRP_MULT [41:37] 204
4-3-19. WP_GRP_SIZE [36:32] 204
4-3-20. WP_GRP_ENABLE [31] 204
4-3-21. DEFAULT_ECC [30:29] 204
4-3-22. R2W_FACTOR [28:26] 204
4-3-23. R2W_FACTOR 204
4-3-24. WRITE_BL_LEN [25:22] 205
4-3-25. WRITE_BL_PARTIAL[21] 205
4-3-26. CONTENT_PROT_APP [16] 205
4-3-27. FILE_FORMAT_GRP [15] 205
4-3-28. COPY [14] 205
4-3-29. PERM_WRITE_PROTECT [13] 205
4-3-30. TMP_WRITE_PROTECT [12] 206
4-3-31. FILE_FORMAT [11:10] - File formats 206
4-3-32. ECC [9:8] - ECC type 206
4-3-33. CRC [7:1] 206
4-3-34. CSD field command classes 206
4-3-35. CSD retrieval and host adjustment 208
4-3-36. Card Payload block length and ECC types handling 208

4-4. EXT_CSD register 208
4-4-1. EXT_CSD 209
4-4-2. EXT_SECURITY_ERR [505] - EXT_SECURITY_ERR byte description 214
4-4-3. S_CMD_SET [504] - Card-supported command sets 214
4-4-4. HPI_FEATURES [503] 214
4-4-5. BKOPS_SUPPORT [502] - Background operations support 215
4-4-6. MAX_PACKED_READS [501] 215
4-4-7. MAX_PACKED_WRITES [500] 215
4-4-8. DATA_TAG_SUPPORT [499] 215
4-4-9. TAG_UNIT_SIZE [498] 215
4-4-10. TAG_RES_SIZE [497] 216
4-4-11. CONTEXT_CAPABILITIES [496] - Context Management Context Capabilities 216
4-4-12. LARGE_UNIT_SIZE_M1 [495] 216
4-4-13. EXT_SUPPORT [494] - EXT_CSD Register Support 216
4-4-14. SUPPORTED_MODES [493] - SUPPORTED_MODES 216
4-4-15. FFU_FEATURES [492] 217
4-4-16. OPERATION_CODES_TIMEOUT [491] - MODE_OPERATION_CODES timeout definition 217
4-4-17. FFU_ARG [490-487] 217
4-4-18. BARRIER_SUPPORT [486] 217
4-4-19. CMDQ_SUPPORT [308] 217
4-4-20. CMDQ_DEPTH [307] 218
4-4-21. NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED [305-302] 218
4-4-22. VENDOR_PROPRIETARY_HEALTH_REPORT [301-270] 218
4-4-23. CARD_LIFE_TIME_EST_TYP_B [269] - Card life time estimation type B value 218
4-4-24. CARD_LIFE_TIME_EST_TYP_A [268] - Card life time estimation type A value 219
4-4-25. PRE_EOL_INFO [267] - Pre EOL info value 219
4-4-26. OPTIMAL_READ_SIZE [266] - Optimal read size value 220
4-4-27. OPTIMAL_WRITE_SIZE [265] - Optimal write size value 220
4-4-28. OPTIMAL_TRIM_UNIT_SIZE [264] - Optimal trim unit size value 220
4-4-29. CARD_VERSION [263-262] 220
4-4-30. FIRMWARE_VERSION [261-254] 220
4-4-31. CACHE_SIZE [252:249] 221
4-4-32. GENERIC_CMD6_TIME [248] - Generic Switch Timeout Definition 221
4-4-33. Power off long switch timeout definition 221
4-4-34. BKOPS_STATUS [246] - Background operations status 221
4-4-35. CORRECTLY_PRG_SECTORS_NUM [245:242] - Correctly programmed sectors number 222
4-4-36. INI_TIMEOUT_AP [241] - Initialization Time out value 222
4-4-37. CACHE_FLUSH_POLICY [240] - Cache Flushing Policy 222
4-4-38. TRIM_MULT [232] - TRIM/DISCARD Time out value 223
4-4-39. SEC_FEATURE_SUPPORT [231] - SEC Feature Support 223
4-4-40. SEC_ERASE_MULT [230] - Secure Erase time-out value 224
4-4-41. SEC_TRIM_MULT [229] - Secure Erase Timeout value 224
4-4-42. BOOT_INFO [228] - Boot information 224
4-4-43. BOOT_SIZE_MULT [226] - Boot partition size 225
4-4-44. ACC_SIZE [225] 225
4-4-44-1. Superpage size 225
4-4-45. HC_ERASE_GRP_SIZE [224] - Erase-unit size 226
4-4-45-1. Erase unit size selection flow 226
4-4-46. ERASE_TIMEOUT_MULT [223] - Erase timeout values 227
4-4-47. REL_WR_SEC_C [222] - Reliable write sector count 228
4-4-48. HC_WP_GRP_SIZE [221] - Write protect group size 228
4-4-49. S_C_VCC[220] and S_C_VCCQ[219] - S_C_VCC, S_C_VCCQ Sleep Current 228
4-4-50. PRODUCTION_STATE_AWARENESS_TIMEOUT [218] - Production State Awareness timeout definition 229
4-4-51. S_A_TIMEOUT [217] - Sleep/awake timeout values 229
4-4-52. SLEEP_NOTIFICATION_TIME [216] - Sleep Notification timeout values 230
4-4-53. SEC_COUNT [215:212] 230
4-4-54. SECURE_WP_INFO[211] 230
4-4-55. MIN_PERF_a_b_ff [210/:205] and MIN_PERF_DDR_a_b_ff [235:234] - R/W access performance values 230
4-4-56. PWR_CL_ff_vvv [203:200] , PWR_CL_ff_vvv[237:236] , PWR_CL_DDR_ff_vvv [239:238]
and PWR_CL_DDR_ff_vvv[253] - Power classes 231
4-4-57. PARTITION_SWITCH_TIME [199] - Partition switch timeout definition 233
4-4-58. OUT_OF_INTERRUPT_TIME [198] - Out-of-interrupt timeout definition 233
4-4-59. DRIVER_STRENGTH [197] - Supported Driver Strengths 233
4-4-60. CARD_TYPE [196] - Card types 234
4-4-61. CSD_STRUCTURE [194] - CSD register structure 234
4-4-62. EXT_CSD_REV [192] - EXT_CSD revisions 235
4-4-63. CMD_SET [191] 235
4-4-64. CMD_SET_REV [189] - Standard MMC command set revisions 235
4-4-65. POWER_CLASS [187] - Power class codes 235
4-4-66. HS_TIMING [185] - HS_TIMING (timing and driver strength) 236
4-4-66-1. HS_TIMING Interface values 236
4-4-67. STROBE_SUPPORT [184] 236
4-4-68. BUS_WIDTH [183] 236
4-4-68-1. Bus Mode Selection 237
4-4-69. ERASEND_MEM_CONT [181] - Erased memory content values 237
4-4-70. PARTITION_CONFIG (before BOOT_CONFIG) [179] — Boot configuration bytes 237
4-4-71. BOOT_CONFIG_PROT[178] — Boot configuration protection 238
4-4-72. BOOT_BUS_CONDITIONS [177] - Boot bus configuration 238
4-4-73. Bus Width and Timing Mode Transition 239
4-4-74. ERASE_GROUP_DEF [175] 240
4-4-75. BOOT_WP_STATUS [174] 240
4-4-76. BOOT_WP [173] — BOOT area Partitions write protection 240
4-4-77. USER_WP [171] — User area write protection 242
4-4-78. FW_CONFIG [169] — FW Update Disable 243
4-4-79. RPMB_SIZE_MULT [168] — RPMB Partition Size 243
4-4-80. WR_REL_SET [167] — Write reliability setting 243
4-4-81. WR_REL_PARAM [166] — Write reliability parameter register 244
4-4-82. SANITIZE_START[165] 245
4-4-83. BKOPS_START [164] 245
4-4-84. BKOPS_EN [163] — Background operations enable 245
4-4-85. RST_n_FUNCTION [162] — H/W reset function 245
4-4-86. HPI_MGMT [161] — HPI management 246
4-4-87. PARTITIONING_SUPPORT [160] — Partitioning Support 246
4-4-88. MAX_ENH_SIZE_MULT [159:157] — Max. Enhanced Area Size 247
4-4-89. PARTITIONS_ATTRIBUTE [156] — Partitions Attribute 247
4-4-90. PARTITION_SETTING_COMPLETED [155] — Partition Setting 247
4-4-91. GP_SIZE_MULT_GP0 - GP_SIZE_MULT_GP3 [154:143] — General Purpose Partition Size 248
4-4-92. ENH_SIZE_MULT [142:140] — Enhanced User Data Area Size 248
4-4-93. ENH_START_ADDR [139:136] — Enhanced User Data Start Address 249
4-4-94. SEC_BAD_BLK_MGMNT [134] — Secure Bad Block management 249
4-4-95. PRODUCTION_STATE_AWARENESS [133] — PRODUCTION_STATE_AWARENESS states 249
4-4-96. TCASE_SUPPORT [132] 250
4-4-97. PERIODIC_WAKEUP [131] — PERIODIC_WAKEUP 250
4-4-98. PROGRAM_CID_CSD_DDR_SUPPORT [130] — CMD26 and CMD27 in DDR mode Support 251
4-4-99. VENDOR_SPECIFIC_FIELD [127:64] 251
4-4-100. NATIVE_SECTOR_SIZE [63] 251
4-4-101. USE_NATIVE_SECTOR [62] 251
4-4-102. DATA_SECTOR_SIZE [61] 251
4-4-103. INI_TIMEOUT_EMU [60] — Initialization Time out value 252
4-4-104. CLASS_6_CTRL[59] — Class 6 usage 252
4-4-105. DYNCAP_NEEDED [58] 252
4-4-106. EXCEPTION_EVENTS_CTRL [57:56] 252
4-4-106-1. EXCEPTION_EVENTS_CTRL[56] 252
4-4-106-2. EXCEPTION_EVENTS_CTRL[57] 252
4-4-107. EXCEPTION_EVENTS_STATUS [55:54] 252
4-4-107-1. EXCEPTION_EVENTS_STATUS[54] 253
4-4-107-2. EXCEPTION_EVENTS_STATUS[55] 253
4-4-108. EXT_PARTITIONS_ATTRIBUTE [53:52] 253
4-4-108-1. First Byte EXT_PARTITIONS_ATTRIBUTE[52] 253
4-4-108-2. Second Byte EXT_PARTITIONS_ATTRIBUTE[53] 253
4-4-109. CONTEXT_CONF [51:37] — CONTEXT_CONF configuration format 254
4-4-110. PACKED_COMMAND_STATUS [36] — Packed Command Status Register 254
4-4-111. PACKED_FAILURE_INDEX [35] 254
4-4-112. POWER_OFF_NOTIFICATION [34] — Valid POWER_OFF_NOTIFICATION values 255
4-4-113. CACHE_CTRL [33] — CACHE ENABLE 255
4-4-114. FLUSH_CACHE [32] — FLUSH CACHE 255
4-4-115. BARRIER_CTRL [31] — BARRIER_CTRL 266
4-4-116. MODE_CONFIG [30] — Valid MODE_CONFIG values 266
4-4-117. MODE_OPERATION_CODES [29] — Valid MODE_OPERATION_CODES values 256
4-4-118. FFU_STATUS [26] — FFU Status codes 256
4-4-119. PRE_LOADING_DATA_SIZE [25-22] 257
4-4-120. 118 MAX_PRE_LOADING_DATA_SIZE [21-18] 257
4-4-121. PRODUCT_STATE_AWARENESS_ENABLEMENT [17] — Production State Awareness Enablement 257
4-4-122. SECURE_REMOVAL_TYPE [16] — Secure Removal Type 258
4-4-123. CMDQ_MODE_EN [15] — Command Queue Mode Enable 258

4-5. RCA register 259

4-6. DSR register 259

4-7. QSR 259

4-8. Authenticated Card Configuration Area 259
4-8-1. Authenticated Card Configuration Area[1] : SECURE_WP_MODE_ENABLE 259
4-8-2. Authenticated Card Configuration Area[2] : SECURE _WP_MODE_CONFIG 260

5. Commands 261
5-1. Command types 261
5-1-1. Command format 261

5-2. Command classes 261
5-2-1. Supported Card command classes (0–56) 262

5-3. Detailed command description 262
5-3-1. Basic commands (class 0 and class 1) 262
5-3-2. Block-oriented read commands (class 2) 264
5-3-3. Class 3 commands 264
5-3-4. Block-oriented write commands (class 4) 265
5-3-5. Block-oriented write protection commands (class 6) 266
5-3-6. Erase commands (class 5) 267
5-3-7. I/O mode commands (class 9) 268
5-3-8. Lock Card commands (class 7) 268
5-3-9. Application-specific commands (class 8) 268
5-3-10. Security Protocols (class 10) 269
5-3-11. Command Queue (Class 11) 269

5-4. Card state transition table 270

5-5. eMMC macro commands 273
5-5-1. Macro commands 273
5-5-2. Legend for command-sequence flow charts 273
5-5-3. SEND_OP_COND command flow chart 274
5-5-4. CIM_SINGLE_CARD_ACQ 275
5-5-5. CIM_SETUP_CARD 276
5-5-6. CIM_READ_BLOCK 277
5-5-7. CIM_READ_MBLOCK 277
5-5-8. CIM_WRITE_BLOCK 278
5-5-9. CIM_WRITE_MBLOCK 278
5-5-10. CIM_ERASE_GROUP 279
5-5-11. CIM_TRIM 279
5-5-12. CIM_US_PWR_WP 280
5-5-13. CIM_US_PERM_WP 281

6. Responses 283
6-1. R1(normal response command) response 283
6-1-1. R1b 283
6-2. R2(CID, CSD register) response 283
6-3. R3(OCR register) response 283
6-4. R4 (Fast I/O) response 284
6-5. R5 (Interruption request) response 284

6-6. Card status 284
6-6-1. Card status table 285
6-6-2. Card Status field/command - cross reference 287
6-6-3. Response 1 Status Bit Valid 288

7. (Normative) Host Controller Interface for Command Queuing 290
7-1. Introduction 290
7-1-1. Background 290
7-1-2. Overview and Scope 290
7-1-3. Feature Summary 290

7-2. Architecture Overview 290
7-2-1. Proposed Host System Architecture, with CQE 290
7-2-2. Task Issuance: Task Descriptor List / Doorbell Register 291
7-2-3. Command Queuing HCI General Architecture 291
7-2-4. Task Processing by Host Hardware 292
7-2-5. Task Selection and Execution 292
7-2-6. Task Completion: Interrupts and Interrupt Coalescing 293
7-2-7. Direct Command (DCMD) Submission 293
7-2-8. Queue-Barrier (QBR) Tasks 293
7-2-9. Halt Feature 293
7-2-10. Error Detection and Recovery 294
7-2-10-1. Handling of Error Conditions in CQE 294

7-3. CQE Data Structures 295
7-3-1. Task Descriptor for Data Transfer Tasks 295
7-3-1-1. Task Descriptor Structure; Lower 64 bits (Data Transfer tasks) 295
7-3-1-2. Task Descriptor Structure; Upper 64 bits 296
7-3-1-3. Task Descriptor for Data Transfer Tasks - Task Descriptor Fields 296

7-4. Transfer Descriptors 296
7-4-1. Transfer Descriptor Structure (32-bit addressing) 296
7-4-2. Transfer Descriptor Structure (64-bit addressing) 297
7-4-3. Transfer Descriptor Fields 297

7-5. Task Descriptor for Direct-Command (DCMD) Tasks 297
7-5-1. Task Descriptor Structure: Lower 64 bits (for DCMD tasks) 298
7-5-2. Task Descriptor Fields (for DCMD tasks) 298
7-5-3. Task Descriptor for Queue-Barrier Task (QBR) 299
7-5-4. Task List 299

7-6. CQE Registers 299
7-6-1. Register Map— CQE Register Map 299
7-6-2. CQBASE+00h: CQVER – Command Queuing Version 300
7-6-3. 3CQBASE+04h: CQCAP – Command Queuing Capabilities 300
7-6-4. CQBASE+08h: CQCFG – Command Queuing Configuration 301
7-6-5. CQBASE+0Ch: CQCTL – Command Queuing Control 301
7-6-6. CQBASE+10h: CQIS – Command Queuing Interrupt Status 302
7-6-7. CQBASE+14h: CQISTE – Command Queuing Interrupt Status Enable 303
7-6-8. CQBASE+18h: CQISGE – Command Queuing Interrupt Signal Enable 303
7-6-9. CQBASE+1Ch: CQIC – Interrupt Coalescing 304
7-6-10. CQBASE+20h: CQTDLBA – Command Queuing Task Descriptor List Base Address 305
7-6-11. CQBASE+24h: CQTDLBAU – Command Queuing Task Descriptor List Base Address 308
7-6-12. CQBASE+28h: CQTDBR – Command Queuing Task Doorbell 308
7-6-13. CQBASE+2Ch: CQTCN – Task Completion Notification 307
7-6-14. CQBASE+30h: CQDQS – Card Queue Status 307
7-6-15. CQBASE+34h: CQDPT – Card Pending Tasks 307
7-6-16. CQBASE+38h: CQTCLR – Task Clear 307
7-6-17. CQBASE+40h: CQSSC1 – Send Status Configuration 1 308
7-6-18. CQBASE+44h: CQSSC2 – Send Status Configuration 2 309
7-6-19. CQBASE+48h: CQCRDCT – Command Response for Direct-Command Task 309
7-6-20. CQBASE+50h: CQRMEM – Response Mode Error Mask 309
7-6-21. CQBASE+54h: CQTERRI - Task Error Information 310
7-6-22. CQBASE+58h: CQCRI – Command Response Index 311
7-6-23. CQBASE+5Ch: CQCRA – Command Response Argument 311

7-7. Command Queuing Interrupt in eMMC Host Controller 311
7-7-1. Normal Interrupt Status Register (Offset 030h) 311
7-7-2. Normal Interrupt Status Enable Register (Offset 034h) 311
7-7-3. Normal Interrupt Signal Enable Register (Offset 038h) 312

7-8. Command Queue: Command Flows (Informative) 312
7-8-1. Queuing a Transaction (CMD44+CMD45) 312
7-8-1-1. Queuing a transaction 312
7-8-2. Checking the Queue Status (SEND_STATUS - CMD13) 312
7-8-3. Execution of a Queued Task (CMD46/CMD47) 312
7-8-3-1. Execution of a queued task 313

7-9. Theory of Operation (Informative) 313
7-9-1. Command Queuing Initialization Sequence 313
7-9-2. Task Issuance Sequence 313
7-9-3. Task Queuing Sequence 314
7-9-4. Task Completion Sequence 314
7-9-5. Task Execution and Completion Sequence 315
7-9-6. Task Discard Sequence (inc. Halting CQE) 315
7-9-7. Task Discard and Clear Sequence Diagram 315

7-10. Error Detect and Recovery 316

8. eMMC 주요 단어 설명 318

도서 정보

책 소개

이 책은 기존의 eMMC 제품 사양서를 좀 더 쉽게 이해시키기 위해 고안되었습니다. 기존의 스펙을 회사 내의 엔지니어가 이해하는 데에는 최소 3개월에서 6개월 이상이 걸리게 되어 있습니다. 그 이유는 첫번째는 각 나라별 모국어가 아닌 공용어인 영어로 제작되어 있기 때문에, 외국어를 재 번역하고 이해하는 데에 시간이 오래 걸리게 되며, 개별 번역 능력의 차이 때문에 의미를 모든 사람이 정확하게 번역한다는 보증도 없습니다. 그로 인해 엔지니어 간에 다양한 이해의 오류, 커뮤니케이션 에러가 발생하게 됩니다. 두번째는 학생처럼 공부만 할 수 있는 조건에서 일하고 있는 엔지니어는 세상 어느 회사에도 존재하지 않습니다. 하루 종일 업무에 시달리다가 비어있는 시간 또는 업무를 하면서 연관된 부분에 대해서만 공부하게 되는데, 그렇다보니, 전체의 내용을 공부하고 이해하고 있는 엔지니어는 사실 찾기가 힘듭니다. 이렇다보니 시간이 지나가도 스펙의 내용을 다 이해하지 못하게 되니, 부족한 지식으로 인해 주의의 사람들로부터 따가운 시선을 받는 경우가 종종 발생하게 됩니다. 세번째는 스펙이 잘 구성되어 있지만, 그 정렬 방식이 순차적, 비 순차적으로 구성되다보니, 현재 보고 있는 스펙을 이해하기 위해서는 갑자기 뒤로 갔다가 앞으로 갔다가를 반복하게 됩니다. 그로 인해 가독성이 떨어지게 되고, 이해의 정도가 낮아지는 문제가 발생합니다.
회사는 높은 연봉을 주고 엔지니어를 고용했는데, 모든 엔지니어들이 제품의 스펙을 이해하는 데 적어도 반년이나 걸린다면 회사에서 지불하고 있는 비용 낭비는 평균 연봉에 엔지니어 수의 곱하기 만큼 발생하게 됩니다. 불필요한 개발 비용 낭비 및 개발 기간 증가는 회사에게는 또 다른 부담을 안겨주게 됩니다.
이러한 문제점을 해결하기 위해서, 이 책에서는 eMMC의 표준 스펙을 각 나라의 모국어로 번역하고, 구성의 배열 방식을 순차적으로 정렬하여, 기본 스펙을 보았을 경우 보다 좀 더 빨리, 좀 더 쉽게 이해할 수 있게 하는 목표로 제작되었습니다. (단, 그림이 있는 부분은 여러 언어로 제작하는 데 있어서 재활용성을 위해서 영어를 그대로 사용하였으니, 양해를 부탁드립니다.)

책의 정렬의 방식은 3 가지 방식을 사용합니다.
첫번째 방식은 개요 → HW → State diagram -> Register -> CMD 순서로 정렬합니다. 사람으로 비유하자면, 몸을 구성한 부분을 설명한 후에 뇌가 어떻게 몸의 각 부분을 제어하는지를 설명하면 이해하는 데 좀 더 빨라지게 됩니다.
두번째는 상관관계가 있는 내용은 같은 곳에 위치시켜서 책 내에서 이곳 저곳 돌아다니지 않고, 한 곳에서 모두 볼 수 있도록 구성하였습니다.
세번째는 그 외에는 기존의 스펙이 구성해놓은 배치를 크게 변경하지 않을 것입니다. 스펙이 만들어질 때도 여러 고려 후 제작되었기 때문에, 이미 많은 부분이 잘 정렬되어 있습니다.

이 책을 통해서 eMMC를 회사에서 개발하는 엔지니어에게는 근무시간에 부족했던 스펙 공부를 빠른 시간에 할 수 있도록 돕기를 바라며, 반도체 관련 회사에 취업하시려는 취업 준비생 분들에게는 메모리 반도체에 있어서 가장 기초적이면서 근본적인 eMMC를 공부하시어 바라시는 회사에 합격하시길 기원합니다.
이 책은 JESD84-B51A을 참고하여 제작되었습니다.